J. Phys. IV France
Volume 08, Numéro PR3, June 1998Proceedings of the 3rd European Workshop on Low Temperature Electronics
|Page(s)||Pr3-29 - Pr3-32|
J. Phys. IV France 08 (1998) Pr3-29-Pr3-32
Optimization of deep-submicrometer temperature scalable MOSFET's based on two-dimensional numerical simulationJ. Xu1 and M.-C. Cheng2
1 Advanced Materials Research Institute, University of New Orleans, LA 70148, U.S.A.
2 Department of Electrical Engineering and Advanced Materials Research Institute, University of New Orleans, LA 70148, U.S.A.
Lowering temperature effects on the performance of submicron and deep-submicron MOSFET's are studied systematically based on two dimensional numerical simulation. The simulation approach features the energy transport model for both electrons and holes in conjunction with an appropriate model for incomplete ionization for impurities at low temperature. A novel design methodology has been developed for optimization of high speed temperature scalable MOS devices operating at low voltage based on the numerical simulation results. Using this new design guideline, together with the conventional constant electric field scaling down theory for MOS devices, high speed deep-submicron CMOS digital circuits can be achieved at low supply voltages.
© EDP Sciences 1998