Optimization of deep-submicrometer temperature scalable MOSFET's based on two-dimensional numerical simulation

J. Xu; M.-C. Cheng

doi:doi:10.1051/jp4:1998307

Numéro		J. Phys. IV France Volume 08, Numéro PR3, June 1998 Proceedings of the 3^rd European Workshop on Low Temperature Electronics WOLTE 3


Page(s)		Pr3-29 - Pr3-32
DOI		https://doi.org/10.1051/jp4:1998307

Proceedings of the 3^rd European Workshop on Low Temperature Electronics
WOLTE 3

J. Phys. IV France 08 (1998) Pr3-29-Pr3-32
DOI: 10.1051/jp4:1998307

Optimization of deep-submicrometer temperature scalable MOSFET's based on two-dimensional numerical simulation

J. Xu¹ and M.-C. Cheng²

¹ Advanced Materials Research Institute, University of New Orleans, LA 70148, U.S.A.
² Department of Electrical Engineering and Advanced Materials Research Institute, University of New Orleans, LA 70148, U.S.A.

Abstract
Lowering temperature effects on the performance of submicron and deep-submicron MOSFET's are studied systematically based on two dimensional numerical simulation. The simulation approach features the energy transport model for both electrons and holes in conjunction with an appropriate model for incomplete ionization for impurities at low temperature. A novel design methodology has been developed for optimization of high speed temperature scalable MOS devices operating at low voltage based on the numerical simulation results. Using this new design guideline, together with the conventional constant electric field scaling down theory for MOS devices, high speed deep-submicron CMOS digital circuits can be achieved at low supply voltages.