J. Phys. IV France
Volume 12, Numéro 3, May 2002
Page(s) 51 - 56

J. Phys. IV France
12 (2002) Pr3-51
DOI: 10.1051/jp420020035

MOSFET modeling and parameter extraction for low temperature analog circuit design

P. Martin1, M. Bucher2 and C. Enz3

1  CEA-LETI, 17 rue des Martyrs, 38054 Grenoble cedex 9, France
2  National Technical University of Athens, GR 15773 Zographou, Athens, Greece
3  CSEM, 2007 Neuchâtel, Switzerland

SPICE parameters needed for simulation of CMOS readout circuits used in infrared image sensors cooled at low temperature are extracted using a specific MOSFET model based on the EKV 2.6 compact charge model. It is used below 200 K and is very well adapted to analog simulation in weak and moderate inversion regimes. It was successively applied on different CMOS processes from different foundries. The model's performance is demonstrated in this work for a 0.35 $\mu$m N + single gate process. Experimental results on the evolution of the low frequency noise and the transistor matching parameters between 300 K and 77 K are also presented. Contrary to the NMOS transistors, the threshold voltage differences of buried channel PMOS transistors are less scattered as the temperature is lowered. The same trend with temperature is observed on the flicker noise parameter.

© EDP Sciences 2002