Cryogenic operation of sub-30 nm nMOSFETs: Impact of device architecture

G. Bertrand; S. Deleonibus; D. Souil; B. Previtali; C. Caillat; G. Guégan; M. Sanquer; F. Balestra

doi:doi:10.1051/jp420020034

Numéro		J. Phys. IV France Volume 12, Numéro 3, May 2002


Page(s)		45 - 49
DOI		https://doi.org/10.1051/jp420020034

J. Phys. IV France 12 (2002) Pr3-45
DOI: 10.1051/jp420020034

Cryogenic operation of sub-30 nm nMOSFETs: Impact of device architecture

G. Bertrand^{1, 2}, S. Deleonibus¹, D. Souil^{1, 2}, B. Previtali¹, C. Caillat¹, G. Guégan¹, M. Sanquer¹ and F. Balestra²

¹ CEA-LETI, 17 rue des Martyrs, 38054 Grenoble cedex 9, France
² Institut de Microélectronique, d'Électromagnétisme et de Photonique (IMEP), 23 rue des Martyrs, BP. 257, 38016 Grenoble cedex 1, France

Abstract
Characteristics of carrier transport are analyzed on sub 30nm NMOSFETs at temperature ranging from 300 K to 20 K. In the on-state regime, degradation of the low field mobility on short channel transistors limits velocity overshoot and ballistic transport occurrence. Nevertheless, due to the drastic reduction of the subthreshold swing, large improvement of the Ion/Ioff trade-off is observed. Thus low temperature operation allows transistors to operate closer to their limit. In the linear regime ( $\rm Vd<10$ mV), short channel transistors exhibits oscillations on the Id-Vg characteristics that remain up to 75 K. These oscillations should be due to state assisted tunneling current.