J. Phys. IV France
Volume 12, Numéro 3, May 2002
Page(s) 61 - 64

J. Phys. IV France
12 (2002) Pr3-61
DOI: 10.1051/jp420020037

Parasitic conduction in a 0.13  $\mu$m CMOS technology at low temperature

A. Mercha, J.M. Rafi, E. Simoen, E. Augendre and C. Claeys

IMEC, Kapeldreef 75, 3001 Leuven, Belgium

Low temperature measurements at 4.2 K and 77 K are performed on n- and p-MOSFETs of a 0.13  $\mu$m CMOS technology. Two parasitic current contributions are identified in the subthreshold regime and strong inversion at 4.2 K. The first one is related to a parasitic parallel conduction inherent to Shallow Trench Isolation. Whereas the second one, resulting in a second peak in the linear transconductance, is discussed in terms of a stronger impact of substrate majority carriers due to a higher substrate resistivity at 4.2 K. The measured substrate current in n-MOSFETs is probably originating from electrons tunneling from the substrate valence band to the gate. At 4.2 K, the substrate current induces a reduction of the threshold voltage resulting in the measured "kink" of the $\rm I_D(V_G)$ characteristic and the second transconductance peak at low drain bias.

© EDP Sciences 2002