| Numéro |
J. Phys. IV France
Volume 12, Numéro 3, May 2002
|
|
|---|---|---|
| Page(s) | 31 - 34 | |
| DOI | https://doi.org/10.1051/jp420020032 | |
J. Phys. IV France 12 (2002) Pr3-31
DOI: 10.1051/jp420020032
Low temperature operation of 0.13
m Partially-Depleted SOI nMOSFETs with floating body
M.A. Pavanello1, 2, J.A. Martino1, A. Mercha3, J.M. Rafi3, E. Simoen3, C. Claeys3, 4, H. van Meer3, 4 and K. De Meyer3, 4
1 Laboratorio de Sistemas lntegraveis, University of Sao Paulo, Av. Prof. Luciano Gualberto, Trav. 3 N. 158, 05508-900 Sao Paulo, Brazil
2 Center for Semiconductor Components, State University of Campinas, Campinas, Brazil
3 IMEC, Kapeldreef 75, 3001 Leuven, Belgium
4 E.E. Department, KU Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium
Abstract
An extended low temperature study of 0.13
m Partially-Depleted Silicon-On-Insulator nMOSFETs without body contact is carried out. The impact of HALO doping characteristics
on device output performance is investigated. The electrical properties of the technology are explored in terms of circuit
applications both in digital and analog sense. The occurrence of inherent parasitic bipolar effects is also studied.
© EDP Sciences 2002