Numéro |
J. Phys. IV France
Volume 12, Numéro 3, May 2002
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Page(s) | 19 - 22 | |
DOI | https://doi.org/10.1051/jp420020029 |
J. Phys. IV France 12 (2002) Pr3-19
DOI: 10.1051/jp420020029
Temperature scaling of nanoscale silicon MOSFETs
V. Sverdlov, Y. Naveh and K.K. LikharevState University of New York, Stony Brook, NY 11794-3800, U.S.A.
Abstract
We have combined a 1D model of double-gate MOSFETs with ultrathin intrinsic channel, with a simple model of power consumption
in digital integrated circuits, to calculate the temperature dependence of the minimum total (static + dynamic) power
P and the optimal power supply voltage
. The results are strongly dependent on the circuit speed assumptions. If the current trend of speed scaling with the critical
size reduction is sustained, both
P and
saturate as soon as
T is decreased below ~100 K. On the other hand, if the high speed condition is removed, transistors may operate in the subthreshold
region and minimum value of
P scales as
T2 while the optimum value of
drops as
T. This reduction is, however, limited by thermal fluctuations, leading to a different scaling,
and
, for low temperatures and/or large circuit densities. Because of this limitation, deep cooling of CMOS circuits may make
sense only in very special cases.
© EDP Sciences 2002