Back gate voltage and buried-oxide thickness influences on the series resistance of fully depleted SOI MOSFETs at 77 K

A.S. Nicolett; J.A. Martino; E. Simoen; C. Claeys

doi:doi:10.1051/jp4:1998306

Numéro		J. Phys. IV France Volume 08, Numéro PR3, June 1998 Proceedings of the 3^rd European Workshop on Low Temperature Electronics WOLTE 3


Page(s)		Pr3-25 - Pr3-28
DOI		https://doi.org/10.1051/jp4:1998306

Proceedings of the 3^rd European Workshop on Low Temperature Electronics
WOLTE 3

J. Phys. IV France 08 (1998) Pr3-25-Pr3-28
DOI: 10.1051/jp4:1998306

Back gate voltage and buried-oxide thickness influences on the series resistance of fully depleted SOI MOSFETs at 77 K

A.S. Nicolett¹, J.A. Martino², E. Simoen³ and C. Claeys³

¹ Faculdade de Tecnologia de São Paulo, Brazil
² Laboratório de Sistemas Integráveis, Universidade de São Paulo, Brazil
³ IMEC, Leuven, Belgium

Abstract
This work studies the influence of the back gate voltage on the LDD SOI nMOSFETs series resistance at 300 K and 77 K and corresponding to two different buried oxide thicknesses. The MEDICI simulated results were used to support the analysis. It was observed that for lower buried oxide thickness the influence of the back gate bias is higher, mainly at 77 K. However, this influence becomes negligible when the back interface below the LDD region is inverted and the depletion region in the LDD reaches its maximum saturation value.