| Issue |
J. Phys. IV France
Volume 06, Number C3, Avril 1996
WOLTE 2Proceedings of the Second European Workshop on Low Temperature Electronics |
|
|---|---|---|
| Page(s) | C3-193 - C3-197 | |
| DOI | https://doi.org/10.1051/jp4:1996329 | |
WOLTE 2
Proceedings of the Second European Workshop on Low Temperature Electronics
J. Phys. IV France 06 (1996) C3-193-C3-197
DOI: 10.1051/jp4:1996329
1 Department of Electrical Engineering, University of California, Los Angeles, 405 Hilgard Avenue, Los Angeles, CA 90095-1594, U.S.A.
2 Superconductor Technologies Incorporated, 460 Ward Street, Suite F, Santa Barbara, CA 93111-2310, U.S.A.
© EDP Sciences 1996
Proceedings of the Second European Workshop on Low Temperature Electronics
J. Phys. IV France 06 (1996) C3-193-C3-197
DOI: 10.1051/jp4:1996329
Process Modification for Improved Low Temperature CMOS Performance
C. Hwang1, C. Jenq2, B. Hammond2, J. Gillick1 and J. Woo11 Department of Electrical Engineering, University of California, Los Angeles, 405 Hilgard Avenue, Los Angeles, CA 90095-1594, U.S.A.
2 Superconductor Technologies Incorporated, 460 Ward Street, Suite F, Santa Barbara, CA 93111-2310, U.S.A.
Abstract
Only minimal performance improvement is achievable when a standard, room-temperature CMOS component is cooled down to low temperatures. However, by modifying the process flow, a 2-3x increase in performance is possible. TCAD tools can be used to study and optimize an original, room temperature CMOS process for low temperature operation. By adjusting the low temperature threshold voltage to a room temperature value, CMOS ring oscillator delays drop in half. Even greater improvement is possible if a lower threshold voltage is used.
© EDP Sciences 1996