| Issue |
J. Phys. IV France
Volume 04, Number C6, Juin 1994
WOLTE 1Proceedings of the First European Workshop on Low Temperature Electronics |
|
|---|---|---|
| Page(s) | C6-13 - C6-18 | |
| DOI | https://doi.org/10.1051/jp4:1994602 | |
WOLTE 1
Proceedings of the First European Workshop on Low Temperature Electronics
J. Phys. IV France 04 (1994) C6-13-C6-18
DOI: 10.1051/jp4:1994602
1 Laboratoire de Physique des Composants à Semiconducteurs, URA du CNRS, Institut National Polytechnique de Grenoble, ENSERG, BP. 257, 38016 Grenoble, France
2 Research Center for Integrated Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 724, Japan
© EDP Sciences 1994
Proceedings of the First European Workshop on Low Temperature Electronics
J. Phys. IV France 04 (1994) C6-13-C6-18
DOI: 10.1051/jp4:1994602
Performances and physical mechanisms in sub-0.1 µm gate length LDD MOSFETs at low temperature
F. Balestra1, H. Nakabayashi2, M. Tsuno2, T. Matsumoto2 and M. Koyanagi21 Laboratoire de Physique des Composants à Semiconducteurs, URA du CNRS, Institut National Polytechnique de Grenoble, ENSERG, BP. 257, 38016 Grenoble, France
2 Research Center for Integrated Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 724, Japan
Abstract
The electrical properties of sub-0.1 µm gate length LDD devices are investigated between room and liquid helium temperatures. The strong impact of gate overlapping effects on LDD resistance is shown for these ultra-short channel MOSFETs in a wide temperature range. It is experimentally demonstrated that these mechanisms lead to a substantial enhancement of the driving current when the devices are scaled down, and induce an additional improvement in the case of low temperature operation. Furthermore, the performances of these transistors with LDD structure at low temperature are also discussed in terms of field assisted impurity ionization in the LDD's.
© EDP Sciences 1994