| Numéro |
J. Phys. IV France
Volume 04, Numéro C6, Juin 1994
WOLTE 1Proceedings of the First European Workshop on Low Temperature Electronics |
|
|---|---|---|
| Page(s) | C6-81 - C6-86 | |
| DOI | https://doi.org/10.1051/jp4:1994613 | |
Proceedings of the First European Workshop on Low Temperature Electronics
J. Phys. IV France 04 (1994) C6-81-C6-86
DOI: 10.1051/jp4:1994613
Low temperature CMOS-compatible JFET's
J. VollrathSolid State Electronics Laboratory, Technical University of Darmstadt, Schloβgartenstrasse8, 64289 Darmstadt, Germany
Abstract
JFETs used as input transistors for CMOS preamplifiers can improve the input sensitivity due to their lower 1/f noise. Cryogenic JFET's can be realized by increasing the channel doping concentration to prevent carrier freeze-out. This paper deals with the properties of fabricated cryogenic, CMOS compatible JFET's. Process parameters for a cryogenic JFET technology are presented. Static measurements of these JFET's between room temperature and 4 K made it possible to extract JFET model parameters Vp and β for circuit simulations. These measurement results are compared with the temperature dependence of mobility and ionisation. Noise parameters could be measured at different temperatures with various geometries and doping levels of JFET's.
© EDP Sciences 1994