Characterization and stressing properties of polysilicon TFTs utilizing oxide films deposited using TEOS

Abstract
In this work we investigated the structural and electrical characteristics of SiO₂ films deposited by Low Pressure Chemical Vapor Deposition (LPCVD) using tetraethylorthosilicate (TEOS) under various deposition pressures and temperatures and their application as gate dielectrics in thin film transistors. It was found using Fourier Transform InfraRed spectroscopy (FTIR) that films deposited at temperatures lower than 635 °C are carbon contaminated, so this temperature was considered as the lowest limit for depositing SiO₂ films with an acceptable carbon contamination. The threshold voltage of TFTs utilizing these oxides was correlated with the structural properties of the oxides. The degradation of the TFT transfer characteristics under various stressing gate bias values was studied and the evolution of the electrical parameters with stressing time was determined. The degradation of both the threshold voltage and the subthreshold swing exhibits a logarithmic dependence with stressing time, indicating a charge trapping process occurring in the oxide and at the polysilicon / SiO₂ interface.