Numéro
J. Phys. IV France
Volume 08, Numéro PR3, June 1998
Proceedings of the 3rd European Workshop on Low Temperature Electronics
WOLTE 3
Page(s) Pr3-45 - Pr3-48
DOI https://doi.org/10.1051/jp4:1998311
Proceedings of the 3rd European Workshop on Low Temperature Electronics
WOLTE 3

J. Phys. IV France 08 (1998) Pr3-45-Pr3-48

DOI: 10.1051/jp4:1998311

A new method to extract the effective trap density at the buried oxide/underlying substrate interface in enhancement-mode SOI MOSFETs at low temperatures

M.A. Pavanello and J.A. Martino

LSI, Laboratório de Sistemas Integráveis, Escola Politécnica da Universidade de São Paulo, Av. Prof Luciano Gualberto, Trav. 3 No. 158, CEP 05508-900 São Paulo, Brazil


Abstract
In this work is proposed a new method to extract the effective interface trap density at the buried oxide/underlying substrate interface in SOI nMOSFETs at 77 K. The theoretical basis to develop the proposed method is the substrate effect model. The proposed method was validated by numerical bidimensional simulation and good agreement was obtained between the imposed values in the simulation and the extracted results by the proposed method. The dependence of the proposed method with the process parameters imprecision was also verified. Finally, the method is applied on experimental data.



© EDP Sciences 1998