Low temperature performance of self-aligned "Etched Polysilicon" emitter pseudo-heterojunction bipolar transistors

G. Giroult-Matlakowski; H. Bousseta; B. Le Tron; D. Dutartre; P. Warren; M.J. Bouzid; A. Nouailhat; P. Ashburn; A. Chantre

doi:doi:10.1051/jp4:1994617

Numéro		J. Phys. IV France Volume 04, Numéro C6, Juin 1994 WOLTE 1 Proceedings of the First European Workshop on Low Temperature Electronics


Page(s)		C6-111 - C6-115
DOI		https://doi.org/10.1051/jp4:1994617

WOLTE 1
Proceedings of the First European Workshop on Low Temperature Electronics

J. Phys. IV France 04 (1994) C6-111-C6-115
DOI: 10.1051/jp4:1994617

Low temperature performance of self-aligned "Etched Polysilicon" emitter pseudo-heterojunction bipolar transistors

G. Giroult-Matlakowski¹, H. Bousseta², B. Le Tron², D. Dutartre², P. Warren², M.J. Bouzid², A. Nouailhat¹, P. Ashburn³ and A. Chantre²

¹ CNRS-URA 358, Laboratoire de Physique de la Matière, INSA Bâtiment 502, 20 Av. Albert Einstein, 69621 Villeurbanne cedex, France
² France Telecom, CNET/CNS, BP. 98, 38243 Meylan cedex, France
³ Dept. of Electronics & Computer Science, University of Southampton, S09 5NH, U.K.

Abstract
In this paper we present an investigation of the static performance over the 300K-80K temperature range of pseudo-heterojunction bipolar transistors using an advanced single-polysilicon CMOS compatible self-aligned structure and epitaxial growth for the base and the low doped emitter spacer. These devices exhibit ideal collector currents and non-ideal base currents. By analysing the base leakage current, we have been able to identify the main critical fabrication steps. The bandgap narrowing in the base has been deduced from the temperature dependence of the collector current and the effect of a parasitic boron spike in the base doping profile on the low temperature performance of the transistor has been studied.