| Numéro |
J. Phys. IV France
Volume 02, Numéro C2, Septembre 1991
Proceedings of the Eighth European Conference on Chemical Vapour Deposition / Actes de la 8ème Confèrence Européenne sur les Dépôts Chimiques en Phase Gazeuse
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| Page(s) | C2-437 - C2-444 | |
| DOI | https://doi.org/10.1051/jp4:1991253 | |
Proceedings of the Eighth European Conference on Chemical Vapour Deposition / Actes de la 8ème Confèrence Européenne sur les Dépôts Chimiques en Phase Gazeuse
J. Phys. IV France 02 (1991) C2-437-C2-444
DOI: 10.1051/jp4:1991253
1 CNET, chemin du Vieux Chêne, BP 98, F-38243 Meylan, France
2 TU Mekelweg 4, P.O. Box 5031, NL-2600 GA Delft, The Netherlands
© EDP Sciences 1991
J. Phys. IV France 02 (1991) C2-437-C2-444
DOI: 10.1051/jp4:1991253
PLANARIZED INTERMETAL DIELECTRIC DEPOSITED BY DECR CVD
A. TISSIER1, J. KHALLAAYOUNE1, A. GERODOLLE1 and B. HUIZING21 CNET, chemin du Vieux Chêne, BP 98, F-38243 Meylan, France
2 TU Mekelweg 4, P.O. Box 5031, NL-2600 GA Delft, The Netherlands
Abstract
A low temperature DECR CVD SiO2 process has been developed using a multifactor multiresponse experimental design. The influence of the process parameters ( SiH4 and O2 flow rate, microwave power and RF bias voltage) on the film characteristics has been evaluated allowing deposition of high quality films. The dependency of the via filling efficiency and the planarization level with the RF bias voltage has been studied. In order to optimize the planarization process simulations were carried out using physically motivated models assuming that the phenomenon is described by the superposition of two independent processes : SiO2 deposition and sputter etching. Results on sputter etching simulation are given here.
© EDP Sciences 1991