Numéro
J. Phys. IV France
Volume 03, Numéro C3, Août 1993
Proceedings of the Ninth European Conference on Chemical Vapour Deposition
Page(s) C3-467 - C3-473
DOI http://dx.doi.org/10.1051/jp4:1993365
Proceedings of the Ninth European Conference on Chemical Vapour Deposition

J. Phys. IV France 03 (1993) C3-467-C3-473

DOI: 10.1051/jp4:1993365

Electrical properties of interlevel deposited oxides related to polysilicon preparation

C. COBIANU, O. POPA and D. DASCALU

Center of Microtechnology, P.O. Box 38-160, Bucharest 72225, Romania


Abstract
Few papers investigated the electrical properties of interlevel high temperature oxides low pressure chemically vapour deposited (LPCVD HTO) SiO2. Silicon dioxide obtained by the surface reaction between SiH2Cl2 and N2O at 900°C on LPCVD polysilicon shows lower electrical conductivity in comparison to SiO2 thermally grown on polysilicon. It was demonstrated a Fowler-Nordheim mechanism for the electrical conduction through the LPCVD HTO SiO2 interpoly dielectrics (2). This paper studies the effect of deposition temperature (in the range of 530°C-613°C) of LPCVD silicon on the electrical properties of interlevel HTO LPCVD SiO2 films deposited on phosphorus doped layers. Phosphorous drive-in from POCl3 was performed in N2 ambient in order to avoid any interface roughness due to thermal oxidation. The low field electrical conduction through these HTO layers can be about one order of magnitude decreased by reducing the deposition temperature of polysilicon from 560 to 530°C while the currents from high fields are not essentially reduced. Thèse results are explained in terms of surface roughness decrease as a function of lowering of deposition temperature. The breakdown fields of LPCVD HTO SiO2 layers, in the range of 8-10 MV/cm, prove the high quality of the dielectric. It is demonstrated that the dielectric breakdown phenomenon originates in the bulk of LPCVD HTO SiO2 films. Based on this experimental study, an improved technology of interlevel structures for polysilicon floating gate EEPROM devices can be proposed.



© EDP Sciences 1993