Proceedings of the Second European Workshop on Low Temperature Electronics
J. Phys. IV France 06 (1996) C3-231-C3-236
Improvements in GaAs JFETs for Deep Cryogenic OperationT.J. Cunningham
Mail Stop 300-315, Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109, U.S.A.
Gallium arsenide junction field-effect transistors (GaAs JFETs) can be made immune to carrier freeze-out, making such transistors useful for the readout of detector arrays that operate at 4 K. Typical applications require transistors with very low noise and extremely low leakage current. By using a recently developed etchant for GaAs that is highly isotropic, etched GaAs JFETs have fabricated that have a gently tapered edge. This reduces edge fields, which consequently reduces the edge tunneling current, the dominant source of leakage current at 4 K. JFETs with gate leakage currents below 10-15 amps have been fabricated. The fabrication technique, including the isotropic etchant is discussed. The leakage current and noise of these JFETs are presented and compared with previous devices using a conventional etch.
© EDP Sciences 1996