Proceedings of the First European Workshop on Low Temperature Electronics
J. Phys. IV France 04 (1994) C6-31-C6-36
Series resistance effects in submicron MOS transistors operated from 300 K down to 4.2 KE.A. Gutiérrez-D1, L. Deferm2 and G. Declerck2
1 Instituto Nacional de Astrofísica, Optica y Electrónica, INAOE, Integrated Circuit Design Group, P.O. Box 216 & 51, Z.P. 72000, Puebla, Pue, Mexico
2 IMEC, Kapeldreef 75, 3001 Leuven, Belgium
In this paper low temperature electrical characterisation (LTEC) of submicron MOS transistors is proposed as an optional tool to investigate second-order effects. The LTEC allows to prove the link between the carrier multiplication at the source side and the series resistance effects. This link cannot be distinguished when the MOS transistor is operated at room temperature. This way one is able to do a further research on the series resistance effects and their impact on the extraction of the electrical parameters of submicron MOS transistors.
© EDP Sciences 1994