J. Phys. IV France 02 (1991) C2-437-C2-444
PLANARIZED INTERMETAL DIELECTRIC DEPOSITED BY DECR CVDA. TISSIER1, J. KHALLAAYOUNE1, A. GERODOLLE1 and B. HUIZING2
1 CNET, chemin du Vieux Chêne, BP 98, F-38243 Meylan, France
2 TU Mekelweg 4, P.O. Box 5031, NL-2600 GA Delft, The Netherlands
A low temperature DECR CVD SiO2 process has been developed using a multifactor multiresponse experimental design. The influence of the process parameters ( SiH4 and O2 flow rate, microwave power and RF bias voltage) on the film characteristics has been evaluated allowing deposition of high quality films. The dependency of the via filling efficiency and the planarization level with the RF bias voltage has been studied. In order to optimize the planarization process simulations were carried out using physically motivated models assuming that the phenomenon is described by the superposition of two independent processes : SiO2 deposition and sputter etching. Results on sputter etching simulation are given here.
© EDP Sciences 1991